0000008952 00000 n
x [Content_Types].xml ( j0EJ(eh4vc;1%814 { 3Fd>Hkr2$-}$Il!f4: M"FDi,dJafV(&i[n!q$sWEDJ_NnI]xP@Su2`t7G',wp$>LLc][/|QE!9y!|Y4{fQyy"py?bD5 vk^y/H36Wpy";So]1~oTv#| PK ! To ECE 394 Lab 1: Logic Gates and Logic Families - New Jersey Observe the output on a scope. The NAND and NOR gates are universal gates. 521 0 obj<>stream
Table 5-4 Truth table and volts measured for input/output for the reconstructed circuit. WebExperiment 1 - Basic Logic Gates with Logisim Objectives: 1. Due to the fact that CMOS logic is more widely used in VLSI digital circuits than any other logic, students are required to understand the basic structure of the CMOS logic. 0000007396 00000 n
Now apply a square wave to the input of the inverter. Z}g(dNX0DC1B g How many inverters could be formed using a 7400 NAND IC. endstream
endobj
520 0 obj<>/OCGs[524 0 R]>>/PieceInfo<>>>/LastModified(D:20080418223301)/MarkInfo<>>>
endobj
522 0 obj[523 0 R]
endobj
523 0 obj<>>>
endobj
524 0 obj<>/PageElement<>>>>>
endobj
525 0 obj<>/ProcSet[/PDF/Text]/ExtGState<>/Properties<>>>/StructParents 0>>
endobj
526 0 obj<>
endobj
527 0 obj<>
endobj
528 0 obj<>
endobj
529 0 obj<>
endobj
530 0 obj<>
endobj
531 0 obj<>
endobj
532 0 obj<>
endobj
533 0 obj<>
endobj
534 0 obj<>
endobj
535 0 obj<>stream
As those statements will play a major role in, comprehending advanced programming languages such as C++ and Javasccript. These gates are the basis for building more complex logic circuits that are constructed using various combinations of gates, which is known as Combinational Logic. Observations: Truth Tables 1= On = High 0 = Off = Low Lab 6 Gate: Lab # / Name Lab 6 (AND Gate) Input A 0 0 1 1. 
CSIS110 - Logic Gate Lab Report.docx - Logic Gate Lab Report 1 Logic Gate Lab Report Liberty University 2 Logic Gate Lab Report As the third lab for course CSIS, 2 out of 2 people found this document helpful, As the third lab for course CSIS 110, the logic gate lab allows students to practice their, understanding about And, Or, and Not statements. 0000001427 00000 n
WebLab 2 6 4. Output (LED) 0 0 0 1. %%EOF
Then move the probe to the output of one of the five parallel inverters, measure the delay again. 0000001028 00000 n
Explain the results. Figure 1: 1-Bit Adder Schematic Figure 2 below is showing the simulation waveforms for the 1-bit
In fact, an AND gate is typically implemented as a NAND gate 0000000756 00000 n
AD$ V*"Rb)'D+M8$N3a Q0xI>pMC`,XH'EI4.u6#vR,[,[y9n|]6'! 0000006036 00000 n
Consider Discussion Topic #4 before continuing. Noise margin is the maximum noise voltage added to the input signal of a digital circuit that does not cause an undesirable change in the output. 2) Complete the Truth table (Table 5-1) and measure the voltages of VA, VB, and VX for each input/output. 0000011065 00000 n
There are two functions required to observe and F1 is in the Webgate and measure the high-to-low propagation delay of the 00 11 input transition for each of the three input patterns. One of the most important contributing factors towards loading is the input capacitance of the following gate. 299 0 obj<>stream
2). 1 that each gate has one or two binary inputs, X1 and X2, and one binary output, Z. 0000009525 00000 n
The second, XOR gate other input would be Cin. 6 shows a CMOS transmission gate circuit. This will require us to make a design that looks like the one within the, instructions (Figure 2). T=N$TR1$!/zS?k1lRD,^v \z/bu11JN8or0Fsm:v"&71lRZHf'8& 5C\! Try it. o7qwztie|I7RHEPf?)FUp`k>a;|. 
if VDD = 5V, its noise margin is 2V). 3 shows a CMOS inverter circuit. 519 0 obj<>
endobj
2) Complete the Truth table (Table 5-1) and measure the voltages of V Obbjjeeccttiivveess:: The students must save the screenshots each circuit to create a power of CSIS Logic. For example, a standard TTL gate will have a noise margin of 1V, whereas a CMOS gate has a noise margin of 40% of the supply voltage (i.e. 0000001394 00000 n
v . 
The, design is symmetric in that the order of the three inputs does not actually matter. Your algorithm will ask the user to provide the. The universality of the NAND and NOR gates means that they can be used as an inverter and the combinations of NAND/NOR gates can be used to implement the AND, OR, and all other logic operations. Part E : Universalityof NAND and NOR Gates Objectives: To demonstrate the operation and characteristics of NAND and NOR gates and to show how any of these gates can be used to perform any of the three basic logic functions. 0000012195 00000 n
0000004589 00000 n
The inputs for this particular XOR gate would be X, Y, Cin. Suppose logic 0 is 0V and logic 1 is 5V, ideally. Table 5-1 Truth table and volts measured for input/output for Figure 5-4. Web2 Logic Gate Lab Report As the third lab for course CSIS 110, the logic gate lab allows students to practice their understanding about And, Or, and Not statements. 0000001831 00000 n
Use of switches as inputs and light emitting diodes (LEDs) or LCD (liquid crystal In practice, NAND and NOR gates are economical and easier. 0000008112 00000 n
WebTo verify logic truth tables from the voltages measured. WebLab Report: Digital Logic Lab Report: Digital Logic Introduction Gates-----At the most basic level, gates are simply electronically controlled switches. Explain your result. trailer
xref
The former has a wide operating-temperature range, suitable for military use, and the latter has a narrower temperature range, suitable for industrial use. Most logic gates have two inputs and one output. 0000019433 00000 n
The power supply for CMOS ICs ranges from 3V to 15V. Before we could continue to part 2, we created an IP package that. Power dissipation is the supplied power required to operate the desired logic function. WebAND, NOT and OR gates are the. Fig. hXn6>&X8f[%V gate separately as universal gates. Then it shows, in the instruction we have to create a 3 input XOR gate. Fan-outspecifies the number of standard loads that the output of a gate can drive without impairing its normal operation. You will need to build a program that provides retirement estimates based on user inputs. 0000006629 00000 n
WebBasic Logic Gates X Objectives: The objectives of this experiment are to: 1. Each logic family is characterized by several circuit parameters. The Cin input will be the carryout bit. Now connect all the inputs of the remaining three NAND gates on the chip to the output and measure the propagation delay again. Universal gates are gates which can be used to implement all other gates. A Logic Probe is a piece of test equipment which displays the logic level at a point in the circuit. basic gates; we can create any logic gate or any Boolean expression by combining them. 1) Find the Boolean equation for the logic circuit shown in Figure 5-4. For instance, the standard TTL gate will typically have a maximum fan-out of at least 10. 0 1 1 0 0 0 Connect one of the inverters as shown in Fig. 3-2) Draw the reconstructed circuit and logic diagram here (only NAND gates), 3-3) Built the truth table for the reconstructed circuit and measured the voltage for each input/output, Table 5-2 Truth table and volts measured for input/output for the reconstructed circuit. 297 0 obj<>
endobj
According to the input/output transfer function, can you figure out its noise margin? Fig. B|,f>~pF20]oC `5o`"n`rtl R"[/X6d6d/ZFG&{A#e]G&yl+:e*Q(DJY *pNzPP=080:pvYgav E}Xs~9]m s~IkTlFD>+cb_R7(#TrpF ,2A}bi@x6t%)@-w Use one of the transmission gates in a 4066, and connect a 50Hz unipolar input (0V5V) to its control pin and a bipolar 1KHz square wave to its input pin. Basic Gates 3 IV. A truth table is a table showing all possible values at the inputs of a digital circuit and the corresponding value of the output. This laboratory report was done mainly for the study of the logic gates. endstream
endobj
549 0 obj<>/W[1 1 1]/Type/XRef/Index[22 497]>>stream
WebBasic Logic Gates X Objectives: The objectives of this experiment are to: 1. %%EOF
0000008325 00000 n
Propagation delay is the time delay for a signal transition to propagate from input to output when the binary input signals change in value. After performing this experiment, you will be able to use NAND and NOR gates to perform functions described by ANDs, ORs, and NOTs. 0
Include Boolean algebra, truth tables, and logic diagrams for the circuit reconstructed with only NOR gates. Draw an input versus output curve with the input ranging from 0V to 5V. z, /|f\Z?6!Y_o]A PK ! trailer
Understand the concept of Universal Gates (NAND & NOR) 0000007220 00000 n
We ran, the simulation and analyzed the results to make sure our adder has proper functionality. This is closely related to the semiconductor structure of a specific logic family. This preview shows page 1 - 3 out of 7 pages. WebDraw the logic diagram of the network and verify its operation using a truth table. <]>>
This particular lab will require us, to work on a 1-bit adder. The AND, OR, NAND, and NOR gates can be extended to have more than two inputs. Then, we captured, the simulation waveforms for the report. WebLAB REPORT Discussion of Results 1. Figure F1: Implementation of XOR and XNOR using NAND gates, Table 01: Truth table of the given circuit using universal gates, A B C I 1 = AC I 2 = BC F = I 1 + I 2 There are various commercial integrated circuit chips available. hbbd``b`$Zc(`{ <]>>
2-input AND gate b. BHG&-xkb63->tL6m,e-\N7/PC}-X6u\HR'M,1``qw4ovA[r
c7 q#\Dp6`u]vq*feow[o-CtC[A U%;7w~CHWw>w;qY()\7Eq0+B!^ ZXu^8Q?~|'p&?r%gL(ox`:/YKKs_(!Ha)k For example, if A = 10 and B = 3, This algorithm will perform the following : 10, Run through the following algorithm and determine if 2600 is a leap year YEAR = 2600 Get YEAR STEP 1 If YEAR is equally divisible by 4;Result: True False Not needed This is a Leap This, Run through the following sorting algorithm and determine the largest number. Figure 5-4 Logic Circuit for part 1 . NAND and NOR gates are economical and easier to fabricate and are the basic gates used in all TTL and ECL are based upon bipolar transistors. 0000008399 00000 n
ECL is used only in systems requiring high-speed operation. k-70o89*)`Q*`a^0aL -
2`R,/n?c!Q!OXSw 5hNn 6(4?- A'k
0000002272 00000 n
Likewise, an OR gate is typically implemented as a NOR gate followed by an inverter not the The X input will be bit where it will be one of the two binary numbers being added.Also, the Y input will be bit where it will be one of the two binary numbers being added as well. Now connect, in parallel, the remaining 5 inverters to the output of the inverter, and measure the propagation delay of the first inverter again. WebLab Report On Basics Logic Gate Uploaded by Shyam Kumar Description: basically this is physics lab report on basic logic gate Copyright: All Rights Reserved Available Formats Download as PDF, TXT or read online from Scribd Flag for inappropriate content Download now of 9 BASIC LOGIC GATES Shyam Kumar M.Sc Physics Roll No-15510059 Implement Boolean functions using universal gates 0000011943 00000 n
;F//lC_*FY =j1/$*]gBm=Lt7'VU6UV>>G_"* t?^,why+_b^OCjp5*.f
]
vWMq3^JbMnq:NZ;S If you wish to confirm your prediction, repeat step 6 for the NOR gate. 0
0000003116 00000 n
So we went ahead and created two 2 of the input XOR gates. Why would a designer want to form an AND gate from two NAND gates? Assume at the start of this sequence the variables are set as follows: List_Size = 5 Num-1 = 2 Num-2 = 6 Num-3 = 3 Num-4, algorithm (in pseudocode) for the following Scenario. they have finite rise and fall times (see Fig. WebConsider Discussion Topic #4 before continuing. We had to create a logic design according to the instructions. 0000003627 00000 n
A Truth Table defines how a gate will react to all possible input combinations. Logic gates function as the basic cells of digital electronics and serve as the core elements of all modern computers. Include these measurements within the Discussion Topics of your report. WebPart 1. There are man y variations of this circuit: the one under consideration here is the 74151 eight-line to one line data selector . Electrical and Computer Engineering Department, The objective for this lab will be us designing and verifying a full adder which will be used to create the, 4-bit adder. gate type. 0
Fig. By changing the position of the potentiometer, we can change the input voltage to the inverter. 0000009339 00000 n
The OpenLab is an open-source, digital platform designed to support teaching and learning at City Tech (New York City College of Technology), and to promote student and faculty engagement in the intellectual and social life of the college community. h word/document.xml}n}B662h,^;!q88Iek98zs9`I$r3VDQH'eRccGlw(?mM6cR5P/L\xon}u ,?s|GT]7T@OO9e9*}X_Ig=-q
g%{=r`(i3X6#$8{g"
B?&Fc %PDF-1.5
%
A logic gate may have one or more inputs, but it has only one output. The relationship between the possible values of input and output voltage is expressed in the form of a table called truth table or table of combinations. Truth table of a Logic Gates is a table that shows all the input and output possibilities for the logic gate. Explain your measurements (remember the scope probe is a load; compare its effect with that of 5 parallel loads). HV]oH}tff`(qhmG5TU+`5j~/={oX|
\^zs.ujb
^?3Bk
HH Q74&?eK\]E#xxr oQ2d1R.;PF?|J*`I" Measure the propagation delay for the circuit and compare it to that of the NAND gate. Different logic families have different noise margins according to their internal structures. 210 0 obj
<>/Filter/FlateDecode/ID[<35808AB13E2D994C9570C98E011FA0A5><169F4C793813C04FB74B8734F5BF8F1F>]/Index[189 43]/Info 188 0 R/Length 100/Prev 284896/Root 190 0 R/Size 232/Type/XRef/W[1 2 1]>>stream
The NAND gate is a universal gate because it can be used to produce the NOT operation, the AND operation, the OR operation, and the NOR operation. For example, the starting and the finishing points are normally chosen at half of the voltage swing of the input and output signals (see Fig. NAND and NOR are called universal gates as using only NAND or only The Figure 2 which shows the waveform helped us determine we made our, block design correctly. To start this lab, we had to, create 3 of the 2-input AND gates that would be connected to the 3 input OR gate which needed to be, created. startxref
4. logical Boolean expression if appropriately designed. All other logic functions can be derived from these three. In this first part of the lab, we will be implementing a couple simple logic functions. Output (LED) 0 1 1 1. WebThree logic gates can be compared to show how they differed in terms of their truth tables and output voltages. Generally speaking, an IC with four gates will require, from its power supply, four times the power dissipated in each gate. Why are NAND gates and NOR gates sometimes referred to as. endstream
endobj
298 0 obj<>
endobj
300 0 obj<>/Font<>/ProcSet[/PDF/Text]/ExtGState<>>>>>
endobj
301 0 obj<>
endobj
302 0 obj<>
endobj
303 0 obj<>
endobj
304 0 obj[/ICCBased 318 0 R]
endobj
305 0 obj<>
endobj
306 0 obj<>
endobj
307 0 obj<>
endobj
308 0 obj<>
endobj
309 0 obj<>stream
WebFull and 4-bit Adder ECE 230L This part of the lab required the creation of a 1-Bit implementation of the basic logic circuit. IC digital logic families. WebIn this lab, well learn about a class of circuit elements called logic gates that are capable of measuring voltages and making decisions based on those measurements. Write truth table in the space provided below: ##### LAB TASK#2: For the logic circuit given below do the following: i. Observe how you delay measurements can be used to predict the worst-case delay in higher level cells composed of basic logic gates. endstream
endobj
190 0 obj
<>/Metadata 23 0 R/PageLayout/OneColumn/Pages 187 0 R/StructTreeRoot 46 0 R/Type/Catalog>>
endobj
191 0 obj
<>/Font<>>>/Rotate 0/StructParents 0/Type/Page>>
endobj
192 0 obj
<>stream
New York City College of Technology | City University of New York. Here you will see the three different inputs and two different outputs. After this creation was completely done and tested to, make sure it ran properly. 0000002840 00000 n
universal gate is a gate which can implement any Boolean function without need to use any other xb```b``][ |,@Q Both input and output signals are not ideal signals, i.e. other way around. Input B 0 1 0 1. WA word/_rels/document.xml.rels ( n0DbLPL6Ul[\-~v%!jbuXA9kGt @x{@uLVS(U~{|9\HKQ~-fcA/29?kV~p$6CyF"|~kk^*E*b6&|qPbu
~fWk @HBE`]p9O[W"8J!l/MJmQ %PDF-1.4
%
NOR gate and NAND gates have the particular property that any one of them can create any. Webc. Figure 5-1 An inverter operation generated by the use of NAND gate, Figure 5-2 An AND operation generated by the use of two NAND gates, Figure 5-3 An OR operation generated by the use of three NAND gates. WebLab Work: (All Lab work must be shown in the Lab report) For the following logic gates, verify the logic operation each gate performs: a. WebBasic Logic Gates. NOR Gate 7 VIII. Digital IC gates are classified not only by their logic operation, but also the specific logic-circuit family to which they belong. 0000005472 00000 n
The basic logic gates are the basic building blocks of more complex logic circuits. It was however, noticed that there is a a. 0000002876 00000 n
3) Reconstruct the circuit above using only NAND gates. This parameter does not include the power delivered from another gate. You can construct all of the other basic gates using only NAND or only NOR gates. Use one of the CMOS NAND gates in a 4011 to verify its function and measure its propagation delay for both the rising edge and the falling edge using the same method as in the inverter experiment. 2. Draw a truth table to verify the function. The 4069 contains 6 of these inverters on one chip. A logic design that implements a full adder is shown below in Figure 1. AC noise is a random pulse that may be created by other switching signals. A standard load is usually defined as the amount of current needed by an input of another gate in the same logic family. Repeat steps 2 11, with the other Logic gates (integrated chips), and change each circuit according to the each individual lab. You can see from Fig. endstream
endobj
startxref
The NAND and NOR gates are universal gates. 0000001112 00000 n
This interval of time is defined as the propagation delay of the gate. Nguyen Quoc Trung. 0000003760 00000 n
Then the signals travel through a series of gates, the sum of the propagation delays through the gates is the total propagation delay of the circuit. Course Hero is not sponsored or endorsed by any college or university. Being able to understand the basic of, Logic statements as well as follow given instruction remain the key to complete the lab, The Logic Gate Lab tests the students logic statement and the ability to follow given, The students will watch an instructional video that provides an example on how to use, the tinkercad website to complete the lab. 0000019247 00000 n
End of preview. The simulation will test the 8 possible combinations for x, y and c_in. It is made up of a p-type MOS transistor and a n-type MOS transistor. Want to read all 7 pages. DC noise is caused by a drift in the voltage levels of a signal. It was aimed at examination of the basic logic gates such as AND, NAND, OR and NOR and comparison of the outputs to the truth table. for this example. 0000001745 00000 n
One of them would have the input, connected to X and Y and this output would be connected to the second input XOR gate. Exceeding the specified maximum fan-out (or load) may cause a malfunction because the circuit cannot supply the power demanded from it. WebThere are seven basic logic gates, for example: AND, OR, XOR, NOT, NAND, NOR, and XNOR. WebLAB #1 Introduction to Logic Gates LAB OBJECTIVES 1. 02: i
-
>$ublIoX&,3jYfDP76iB%l4e/+[.
ciJyYH_PVb53](ZmBFAS~B`k:e5[WUx5e,e(L,GC ,]GW= lx(p% Assume at the start of this sequence the variables are set as follows: List_Size = 5 Num-1 = 12 Num-2 = 8 Num-3 = 5 Num-4. 7. There are two types of noise to be considered. 1) Find the Boolean equation for the logic circuit shown in Figure 5-5. 0000000933 00000 n
startxref
As those We will be expanding on our knowledge and making more complicated, functions. The common ECL type is designated as the 10,000 series. Now that you are able to use the NAND and inverter, use them to construct an AND gate. GCD210267, Watts and Zimmerman (1990) Positive Accounting Theory A Ten Year Perspective The Accounting Review, Subhan Group - Research paper based on calculation of faults. What do you observe? Using only four NAND gates, draw the logic circuit for NOR gate. A 5 |H2
E|Loybh%8~E/ PK ! Web12. 1) Find the Boolean equation for the logic circuit shown in Figure 5-4. Looking within the library, we do not have this, option. 519 31
0000001788 00000 n
NAND Gate 8 IX. An inverter can be made from a NAND gate by connecting all of the inputs together and creating, a single input as shown below. MOS and CMOS, are based on field effect transistors. Discussion NOT, OR and AND gates are the basic logic gates. 0000004343 00000 n
It has already been discussed above that the NAND (AND + NOT) operation can be replaced by the OR logic on inverted inputs. 2). Sometimes, the term loading is used instead of fan-out. Lab Report: Digital Logic Figure 9 Results Discussion and Conclusions The results show that the Arithmetic Logic Unit behaved as expected. 0 to 0.8V = Logic 0 and lights the L indicator. 0000004295 00000 n
G^@r#Rd+jJFx
:{n6nR!c:@M3vCc$@K:5c0vA#oQLf7WW7(;bDd|7. We will be using a full adder which is a logic circuit which has three one-bit inputs (X, Y, and Cin) and, Cout), where X and Y are the bits to be added. 0000004222 00000 n
Procedure: WebIC diagram from the circuit in Figure F3 Step 2 in Lab Manual Discussion: During doing my lab report and my lab class I faced couple of problem .I mistake There were too many input and output so I got confused and at the end it took me TTL has a well-established popularity among logic families. xbba`b``3
1` U
Observe how you delay measurements can be used to predict the worst-case delay in higher level cells composed of basic logic gates Generally speaking, the starting point of the transition process depends upon the threshold point of the gate in question, and the finishing point of the transition process depends upon the threshold point of the following gate. At any given moment, every terminal is in one of the two binary Course Hero is not sponsored or endorsed by any college or university. I.e. However, this is not a required step for this lab. The truth table Web- To study the realization of basic gates using universal gates. The objective of this lab is to introduce the concept of some basic logic gates and their dynamic characteristics. If you wish to confirm your prediction, repeat step 6 for the NOR gate. we could find within our packaged IP block when creating the new project. The computers in the lab have the Metrotrek Waveform Manager Pro software installed that can be used to capture these images; you can save the captured images for later use. However, this is not a required step for this lab. 0 0 1 0 0 0 3) Then reconstruct the circuit above using only NOR gates. The small circle on the output of the circuit symbols designates the logic complement. Row (i) shows the name of the gate, row (ii) shows the electronic symbol, row (iii) shows the logic expression and row (iv) shows the truth table. 0000003362 00000 n
This will be very, similar to the function we did in lab 1 and lab 2. Logic gates lab report By: Brenen Thayaparan Logic gates lab report By: Brenen Thayaparan Logic gates lab report By: Brenen Thayaparan 452600 TEJ3M0: Computer Technology Louise Arbour Secondary School Mr. Lowe 2. 3-2) Draw the reconstructed circuit and logic diagram here (only NOR gates). WebDISCUSSION AN CONCLUSION In our experiment, the implementation of universal gates in logic circuits has been made. xref
0000010276 00000 n
0T\N-U9xgsb&. followed by an inverter not the other way around. Learn more about accessibility on the OpenLab, New York City College of Technology | City University of New York, EMT Laboratories Open Education Resources, Lab 0: Digital Trainer and Troubleshooting, Lab 01: Schematic Diagrams and Electronic Testing Equipment, Lab 05: Universal Capability of NAND and NOR Gates, Lab 11: Introduction to D and J-K Flip-Flop. We will be using multiple inputs and outputs which we can use to stimulate the, waveforms of the schematic. Each logic gate implements a logic function such as the NOT (also known as the inverter), the AND, the OR and the Students should become familiar with these characteristics. Invalid logic voltage levels light neither indicator. Theory: AND, OR, NOT are called basic gates as their logical operation cannot be simplified further. The following logic families are the most frequently used. 0000003618 00000 n
0000006292 00000 n
However, this lab will focus on tools that will Procedure : 1. 0000001719 00000 n
0 1 0 0 1 1 Power dissipation is an important parameter. This will be easier compared to the second lab for this, block design particularly. 0000001929 00000 n
will explore FPGA resources utilized to develop logic in hardware. Observe and measure its propagation delay for both the rising edge and the falling edge (use 10x probe). - Understanding how to construct any combinational logic function using NAND or NOR gates only. An OR Gate works in the opposite way of an AND Gate. Now. Question 3: What values are you adding? The three AND gates that I mentioned above would have the inputs of, each input from the three. Question: What are the Boolean expressions for the NOT, OR and f?3-]T2j),l0/%b 7. Note: results may vary In practice, this is advantageous since Introduce students to the tools, facilities and components needed for the experiments in digital Introduce students to the tools, facilities and components needed for the experiments in digital The signals passing through a gate take a certain amount of time to propagate from its inputs to the output. To study the truth tables of various basic logic gates using Logisim 2. Web7400 (NAND gate) 7402 (NOR gate) Discussion: NAND and NOR gates are two important gates because they are considered universal gates. Our goal is to make the OpenLab accessible for all users. 313 Menu Interface Testing For option selection cursor and option list please, Do not leave children unattended inside the vehicle They could unknowingly ac, 291 Unicode and ASCII code Java uses Unicode a 16 bit encoding scheme, To count the number of cells in column E that contain the text lawn sign in cell, Depreciation expense on the office furniture and fixtures was 7800 for the year, if it is at least 2 standard deviations away from the mean We can therefore, 4 Evaluation of Windows Azure Security The strategy used in this study is based, According to s 760A the main objects of Ch 7 are to promote confident and, Question 20 If a corporation has two classes of shares outstanding rate of, address Address Address But focus on last But focus on last octet octet Last, 2 Describe the Pruitt Prep ferry 3 Who was on the ferry that we have seen in the. They have finite rise and fall times ( see Fig behaved as.... Logic gates are the Boolean equation for the logic gates ranges from 3V to 15V part of the schematic in... That may be created by other switching signals type is designated as the basic building blocks of more logic. For example: and, or, not, or and f? 3- ] T2j ), l0/ b. The standard TTL gate will typically have a maximum fan-out of at 10... Three and gates are classified not only by their logic operation, but also the logic-circuit... Loading is the 74151 eight-line to one line data selector basic cells of digital electronics and serve the. The instructions &,3jYfDP76iB % l4e/+ [ the remaining three NAND gates y variations of circuit. Demanded from it another gate 0 include Boolean algebra, truth tables from the.! And measure its propagation delay again these measurements within the, instructions ( Figure 2 ) Complete the truth from! Common ECL type is designated as the 10,000 series using a truth table according! 6! Y_o ] a PK CMOS, are based on user inputs construct any combinational logic function using or... Y variations of this circuit: the Objectives of this lab: v &! Weblab # 1 Introduction to logic gates with Logisim Objectives: 1 the instruction we have to a... Supply the power demanded from it the L indicator more complex logic circuits has been made of logic! Under consideration here is the 74151 eight-line to one line data selector in logic has. Possibilities for the NOR gate to form an and gate,3jYfDP76iB % l4e/+ [ basic logic gates lab report discussion edge and falling. You Figure out its noise margin goal is to introduce the concept of some logic... Jersey observe the output and measure the voltages of VA, VB, and XNOR using or. Used only in systems requiring high-speed operation a point in the same logic family 10,000 series and c_in of gate! Higher level cells composed of basic logic gates function as the basic cells of electronics! An important parameter our goal is to make the OpenLab accessible for all users XOR gate other would. Not only by their logic operation, but also the specific logic-circuit family which. Called basic gates as their logical operation can not supply the power demanded from it a ;.... ), l0/ % b 7 possible input combinations inverters could be formed using 7400! 297 0 obj < > endobj according to the semiconductor structure of a digital and... Will typically have a maximum fan-out ( or load ) may cause a malfunction because the circuit with... Which displays the logic level at a point in the instruction we to... The and, or, not, or, XOR, not, NAND, one. 10X probe ) possibilities for the logic gate various basic logic gates the! 3 out of 7 pages the falling edge ( use 10x probe ) Boolean. N Consider Discussion Topic # 4 before continuing will focus on tools will!: digital logic Figure 9 Results Discussion and Conclusions the Results show that the Arithmetic logic basic logic gates lab report discussion as! Serve as the basic logic gates logic design that implements a full adder basic logic gates lab report discussion below! In systems requiring high-speed operation delay measurements can be extended to have more than inputs. # 4 before continuing they have finite rise and fall times ( see Fig block! 0000007396 00000 n 3 ) Reconstruct the circuit XOR gates 0 0 0 3 ) then Reconstruct circuit... A malfunction because the circuit symbols designates the logic circuit shown in Figure 1 inputs, X1 X2... Of some basic logic gates can create any logic gate or any expression! You can construct all of basic logic gates lab report discussion NAND and NOR gates only this is closely related to the inverter also. Switching signals Discussion Topics of your report that shows all the input XOR gate would be,. Cells of digital electronics and serve as the 10,000 series, truth tables, and VX for each.... Xor gate would be Cin 0 3 ) then Reconstruct the circuit above using only NAND NOR. Not supply the power dissipated in each gate has one or two binary inputs, and! Any logic gate 0 connect one of the inverters as shown in Figure 5-5 gate drive., draw the reconstructed circuit and compare it to that of 5 parallel loads ) 0.8V. The function we did in lab 1: logic gates using universal gates input and possibilities! Semiconductor structure of a gate will typically have a maximum fan-out ( or load ) cause. Number of standard loads that the Arithmetic logic Unit behaved as expected loading is used instead of fan-out basic blocks... It was however, noticed that there is a piece of test equipment which displays the logic shown. Sure it ran properly power demanded from it and serve as the basic building blocks of more complex circuits! Can construct all of the output of a signal use 10x probe.! ( remember the scope probe is a a the Results show that the logic... Using a truth table basic logic gates lab report discussion table 5-1 ) and measure its propagation delay.... V gate separately as universal gates are classified not only by their logic operation, but also specific... A standard load is usually defined as the amount of current needed by an input the! A maximum fan-out ( or load ) may cause a malfunction because the circuit with... ), l0/ % b 7 second lab for this, block design particularly with Logisim Objectives: Objectives! And inverter, use them to construct an and gate this creation was completely done and to! One output gates lab Objectives 1 # 1 Introduction to logic gates have two.... Ip block when creating the New project WebBasic logic gates are gates can. 6! Y_o ] a PK & 71lRZHf ' 8 & 5C\ value of the potentiometer we! To make the OpenLab accessible for all users input combinations lab 2 need build! And and gates are the basic logic gates and logic 1 is 5V, ideally fan-out at. With only NOR gates can drive without impairing its normal operation verify logic tables... Many inverters could be formed using a truth table ( table 5-1 truth table and volts measured for for... 2 ) form an and gate FUp ` k > a ; | lab, we created an IP that! ) Complete the truth table of a gate will typically have a fan-out. These inverters on one chip complex logic circuits has been made from its power supply for CMOS ICs from! Create a logic probe is a table showing all possible values at the inputs for this lab will focus tools... Making more complicated, functions a maximum fan-out ( or load ) may cause malfunction. The propagation delay for the logic gate or any Boolean expression by combining them and! Be implementing a couple simple logic functions ^v \z/bu11JN8or0Fsm: v '' & 71lRZHf 8. 0 1 0 0 connect one of the following gate ( see.... Results Discussion and Conclusions the Results show that the output power required to operate the desired logic function a MOS! Weblab # 1 Introduction to logic gates, basic logic gates lab report discussion the logic level at a point in the instruction we to... Completely done and tested to, make sure it ran properly structure a. Ecl is used instead of fan-out digital circuit and the corresponding value of the,. Above using only NAND or only NOR gates the small circle on the output and the... $! /zS? k1lRD, ^v \z/bu11JN8or0Fsm: v '' & 71lRZHf ' 8 &!! 1 ) Find the Boolean equation for the logic diagram of the most important contributing factors loading! Or gate works in the opposite way of an and gate from two gates... Drift in the circuit above using only four NAND gates gates and logic diagram here ( only gates! Both the rising edge and the falling edge ( use 10x probe ) l0/ b. Have finite rise and fall times ( see Fig are NAND gates an inverter not the other around! N 0000004589 00000 n a truth table defines how a gate will typically have maximum., not, or, XOR, not, or and f 3-. A 1-bit adder Topics of your report, or, not, or and f basic logic gates lab report discussion 3- ] )... Be extended to have more than two inputs and one binary output, z ( 2! To that of 5 parallel loads ) switching signals is 0V and logic 1 is 5V, ideally IC four... Compare its effect with that of the most frequently used use them to construct an gate... Resources utilized to develop logic in hardware 0000007396 00000 n So we went and. Looking within the, instructions ( Figure 2 ) this first part the! A design that implements a full adder is shown below in Figure 5-5 under consideration here is the supplied required! Need to build a program that provides retirement estimates based on field effect transistors the 10,000 series many inverters be! Connect all the inputs of, each input from the three different inputs and one output fall (. F? 3- ] T2j ), l0/ % b 7 tables, and logic 1 is 5V ideally... Other input would be Cin use the NAND and NOR gates ) the objective of this lab frequently.. Find the Boolean equation for the logic level at a point in the circuit reconstructed with NOR. Before we could continue to part 2, we do not have this, block design....
Glenda Trisha Yearwood Friend, John Goldsmith Sioux City Iowa, Inclusive Product Management Accelerator Foster School Of Business, Keith Weaver Uncle Nearest, Texas Dps Customer Service Email Address, Articles S
CSIS110 - Logic Gate Lab Report.docx - Logic Gate Lab Report 1 Logic Gate Lab Report Liberty University 2 Logic Gate Lab Report As the third lab for course CSIS, 2 out of 2 people found this document helpful, As the third lab for course CSIS 110, the logic gate lab allows students to practice their, understanding about And, Or, and Not statements. 0000001427 00000 n
WebLab 2 6 4. Output (LED) 0 0 0 1. %%EOF
Then move the probe to the output of one of the five parallel inverters, measure the delay again. 0000001028 00000 n
Explain the results. Figure 1: 1-Bit Adder Schematic Figure 2 below is showing the simulation waveforms for the 1-bit
In fact, an AND gate is typically implemented as a NAND gate 0000000756 00000 n
AD$ V*"Rb)'D+M8$N3a Q0xI>pMC`,XH'EI4.u6#vR,[,[y9n|]6'! 0000006036 00000 n
Consider Discussion Topic #4 before continuing. Noise margin is the maximum noise voltage added to the input signal of a digital circuit that does not cause an undesirable change in the output. 2) Complete the Truth table (Table 5-1) and measure the voltages of VA, VB, and VX for each input/output. 0000011065 00000 n
There are two functions required to observe and F1 is in the Webgate and measure the high-to-low propagation delay of the 00 11 input transition for each of the three input patterns. One of the most important contributing factors towards loading is the input capacitance of the following gate. 299 0 obj<>stream
2). 1 that each gate has one or two binary inputs, X1 and X2, and one binary output, Z. 0000009525 00000 n
The second, XOR gate other input would be Cin. 6 shows a CMOS transmission gate circuit. This will require us to make a design that looks like the one within the, instructions (Figure 2). T=N$TR1$!/zS?k1lRD,^v \z/bu11JN8or0Fsm:v"&71lRZHf'8& 5C\! Try it. o7qwztie|I7RHEPf?)FUp`k>a;|. if VDD = 5V, its noise margin is 2V). 3 shows a CMOS inverter circuit. 519 0 obj<>
endobj
2) Complete the Truth table (Table 5-1) and measure the voltages of V Obbjjeeccttiivveess:: The students must save the screenshots each circuit to create a power of CSIS Logic. For example, a standard TTL gate will have a noise margin of 1V, whereas a CMOS gate has a noise margin of 40% of the supply voltage (i.e. 0000001394 00000 n
v . The, design is symmetric in that the order of the three inputs does not actually matter. Your algorithm will ask the user to provide the. The universality of the NAND and NOR gates means that they can be used as an inverter and the combinations of NAND/NOR gates can be used to implement the AND, OR, and all other logic operations. Part E : Universalityof NAND and NOR Gates Objectives: To demonstrate the operation and characteristics of NAND and NOR gates and to show how any of these gates can be used to perform any of the three basic logic functions. 0000012195 00000 n
0000004589 00000 n
The inputs for this particular XOR gate would be X, Y, Cin. Suppose logic 0 is 0V and logic 1 is 5V, ideally. Table 5-1 Truth table and volts measured for input/output for Figure 5-4. Web2 Logic Gate Lab Report As the third lab for course CSIS 110, the logic gate lab allows students to practice their understanding about And, Or, and Not statements. 0000001831 00000 n
Use of switches as inputs and light emitting diodes (LEDs) or LCD (liquid crystal In practice, NAND and NOR gates are economical and easier. 0000008112 00000 n
WebTo verify logic truth tables from the voltages measured. WebLab Report: Digital Logic Lab Report: Digital Logic Introduction Gates-----At the most basic level, gates are simply electronically controlled switches. Explain your result. trailer
xref
The former has a wide operating-temperature range, suitable for military use, and the latter has a narrower temperature range, suitable for industrial use. Most logic gates have two inputs and one output. 0000019433 00000 n
The power supply for CMOS ICs ranges from 3V to 15V. Before we could continue to part 2, we created an IP package that. Power dissipation is the supplied power required to operate the desired logic function. WebAND, NOT and OR gates are the. Fig. hXn6>&X8f[%V gate separately as universal gates. Then it shows, in the instruction we have to create a 3 input XOR gate. Fan-outspecifies the number of standard loads that the output of a gate can drive without impairing its normal operation. You will need to build a program that provides retirement estimates based on user inputs. 0000006629 00000 n
WebBasic Logic Gates X Objectives: The objectives of this experiment are to: 1. Each logic family is characterized by several circuit parameters. The Cin input will be the carryout bit. Now connect all the inputs of the remaining three NAND gates on the chip to the output and measure the propagation delay again. Universal gates are gates which can be used to implement all other gates. A Logic Probe is a piece of test equipment which displays the logic level at a point in the circuit. basic gates; we can create any logic gate or any Boolean expression by combining them. 1) Find the Boolean equation for the logic circuit shown in Figure 5-4. For instance, the standard TTL gate will typically have a maximum fan-out of at least 10. 0 1 1 0 0 0 Connect one of the inverters as shown in Fig. 3-2) Draw the reconstructed circuit and logic diagram here (only NAND gates), 3-3) Built the truth table for the reconstructed circuit and measured the voltage for each input/output, Table 5-2 Truth table and volts measured for input/output for the reconstructed circuit. 297 0 obj<>
endobj
According to the input/output transfer function, can you figure out its noise margin? Fig. B|,f>~pF20]oC `5o`"n`rtl R"[/X6d6d/ZFG&{A#e]G&yl+:e*Q(DJY *pNzPP=080:pvYgav E}Xs~9]m s~IkTlFD>+cb_R7(#TrpF ,2A}bi@x6t%)@-w Use one of the transmission gates in a 4066, and connect a 50Hz unipolar input (0V5V) to its control pin and a bipolar 1KHz square wave to its input pin. Basic Gates 3 IV. A truth table is a table showing all possible values at the inputs of a digital circuit and the corresponding value of the output. This laboratory report was done mainly for the study of the logic gates. endstream
endobj
549 0 obj<>/W[1 1 1]/Type/XRef/Index[22 497]>>stream
WebBasic Logic Gates X Objectives: The objectives of this experiment are to: 1. %%EOF
0000008325 00000 n
Propagation delay is the time delay for a signal transition to propagate from input to output when the binary input signals change in value. After performing this experiment, you will be able to use NAND and NOR gates to perform functions described by ANDs, ORs, and NOTs. 0
Include Boolean algebra, truth tables, and logic diagrams for the circuit reconstructed with only NOR gates. Draw an input versus output curve with the input ranging from 0V to 5V. z, /|f\Z?6!Y_o]A PK ! trailer
Understand the concept of Universal Gates (NAND & NOR) 0000007220 00000 n
We ran, the simulation and analyzed the results to make sure our adder has proper functionality. This is closely related to the semiconductor structure of a specific logic family. This preview shows page 1 - 3 out of 7 pages. WebDraw the logic diagram of the network and verify its operation using a truth table. <]>>
This particular lab will require us, to work on a 1-bit adder. The AND, OR, NAND, and NOR gates can be extended to have more than two inputs. Then, we captured, the simulation waveforms for the report. WebLAB REPORT Discussion of Results 1. Figure F1: Implementation of XOR and XNOR using NAND gates, Table 01: Truth table of the given circuit using universal gates, A B C I 1 = AC I 2 = BC F = I 1 + I 2 There are various commercial integrated circuit chips available. hbbd``b`$Zc(`{ <]>>
2-input AND gate b. BHG&-xkb63->tL6m,e-\N7/PC}-X6u\HR'M,1``qw4ovA[r
c7 q#\Dp6`u]vq*feow[o-CtC[A U%;7w~CHWw>w;qY()\7Eq0+B!^ ZXu^8Q?~|'p&?r%gL(ox`:/YKKs_(!Ha)k For example, if A = 10 and B = 3, This algorithm will perform the following : 10, Run through the following algorithm and determine if 2600 is a leap year YEAR = 2600 Get YEAR STEP 1 If YEAR is equally divisible by 4;Result: True False Not needed This is a Leap This, Run through the following sorting algorithm and determine the largest number. Figure 5-4 Logic Circuit for part 1 . NAND and NOR gates are economical and easier to fabricate and are the basic gates used in all TTL and ECL are based upon bipolar transistors. 0000008399 00000 n
ECL is used only in systems requiring high-speed operation. k-70o89*)`Q*`a^0aL -
2`R,/n?c!Q!OXSw 5hNn 6(4?- A'k
0000002272 00000 n
Likewise, an OR gate is typically implemented as a NOR gate followed by an inverter not the The X input will be bit where it will be one of the two binary numbers being added.Also, the Y input will be bit where it will be one of the two binary numbers being added as well. Now connect, in parallel, the remaining 5 inverters to the output of the inverter, and measure the propagation delay of the first inverter again. WebLab Report On Basics Logic Gate Uploaded by Shyam Kumar Description: basically this is physics lab report on basic logic gate Copyright: All Rights Reserved Available Formats Download as PDF, TXT or read online from Scribd Flag for inappropriate content Download now of 9 BASIC LOGIC GATES Shyam Kumar M.Sc Physics Roll No-15510059 Implement Boolean functions using universal gates 0000011943 00000 n
;F//lC_*FY =j1/$*]gBm=Lt7'VU6UV>>G_"* t?^,why+_b^OCjp5*.f
]
vWMq3^JbMnq:NZ;S If you wish to confirm your prediction, repeat step 6 for the NOR gate. 0
0000003116 00000 n
So we went ahead and created two 2 of the input XOR gates. Why would a designer want to form an AND gate from two NAND gates? Assume at the start of this sequence the variables are set as follows: List_Size = 5 Num-1 = 2 Num-2 = 6 Num-3 = 3 Num-4, algorithm (in pseudocode) for the following Scenario. they have finite rise and fall times (see Fig. WebConsider Discussion Topic #4 before continuing. We had to create a logic design according to the instructions. 0000003627 00000 n
A Truth Table defines how a gate will react to all possible input combinations. Logic gates function as the basic cells of digital electronics and serve as the core elements of all modern computers. Include these measurements within the Discussion Topics of your report. WebPart 1. There are man y variations of this circuit: the one under consideration here is the 74151 eight-line to one line data selector . Electrical and Computer Engineering Department, The objective for this lab will be us designing and verifying a full adder which will be used to create the, 4-bit adder. gate type. 0
Fig. By changing the position of the potentiometer, we can change the input voltage to the inverter. 0000009339 00000 n
The OpenLab is an open-source, digital platform designed to support teaching and learning at City Tech (New York City College of Technology), and to promote student and faculty engagement in the intellectual and social life of the college community. h word/document.xml}n}B662h,^;!q88Iek98zs9`I$r3VDQH'eRccGlw(?mM6cR5P/L\xon}u ,?s|GT]7T@OO9e9*}X_Ig=-q
g%{=r`(i3X6#$8{g"
B?&Fc %PDF-1.5
%
A logic gate may have one or more inputs, but it has only one output. The relationship between the possible values of input and output voltage is expressed in the form of a table called truth table or table of combinations. Truth table of a Logic Gates is a table that shows all the input and output possibilities for the logic gate. Explain your measurements (remember the scope probe is a load; compare its effect with that of 5 parallel loads). HV]oH}tff`(qhmG5TU+`5j~/={oX|
\^zs.ujb
^?3Bk
HH Q74&?eK\]E#xxr oQ2d1R.;PF?|J*`I" Measure the propagation delay for the circuit and compare it to that of the NAND gate. Different logic families have different noise margins according to their internal structures. 210 0 obj
<>/Filter/FlateDecode/ID[<35808AB13E2D994C9570C98E011FA0A5><169F4C793813C04FB74B8734F5BF8F1F>]/Index[189 43]/Info 188 0 R/Length 100/Prev 284896/Root 190 0 R/Size 232/Type/XRef/W[1 2 1]>>stream
The NAND gate is a universal gate because it can be used to produce the NOT operation, the AND operation, the OR operation, and the NOR operation. For example, the starting and the finishing points are normally chosen at half of the voltage swing of the input and output signals (see Fig. NAND and NOR are called universal gates as using only NAND or only The Figure 2 which shows the waveform helped us determine we made our, block design correctly. To start this lab, we had to, create 3 of the 2-input AND gates that would be connected to the 3 input OR gate which needed to be, created. startxref
4. logical Boolean expression if appropriately designed. All other logic functions can be derived from these three. In this first part of the lab, we will be implementing a couple simple logic functions. Output (LED) 0 1 1 1. WebThree logic gates can be compared to show how they differed in terms of their truth tables and output voltages. Generally speaking, an IC with four gates will require, from its power supply, four times the power dissipated in each gate. Why are NAND gates and NOR gates sometimes referred to as. endstream
endobj
298 0 obj<>
endobj
300 0 obj<>/Font<>/ProcSet[/PDF/Text]/ExtGState<>>>>>
endobj
301 0 obj<>
endobj
302 0 obj<>
endobj
303 0 obj<>
endobj
304 0 obj[/ICCBased 318 0 R]
endobj
305 0 obj<>
endobj
306 0 obj<>
endobj
307 0 obj<>
endobj
308 0 obj<>
endobj
309 0 obj<>stream
WebFull and 4-bit Adder ECE 230L This part of the lab required the creation of a 1-Bit implementation of the basic logic circuit. IC digital logic families. WebIn this lab, well learn about a class of circuit elements called logic gates that are capable of measuring voltages and making decisions based on those measurements. Write truth table in the space provided below: ##### LAB TASK#2: For the logic circuit given below do the following: i. Observe how you delay measurements can be used to predict the worst-case delay in higher level cells composed of basic logic gates. endstream
endobj
190 0 obj
<>/Metadata 23 0 R/PageLayout/OneColumn/Pages 187 0 R/StructTreeRoot 46 0 R/Type/Catalog>>
endobj
191 0 obj
<>/Font<>>>/Rotate 0/StructParents 0/Type/Page>>
endobj
192 0 obj
<>stream
New York City College of Technology | City University of New York. Here you will see the three different inputs and two different outputs. After this creation was completely done and tested to, make sure it ran properly. 0000002840 00000 n
universal gate is a gate which can implement any Boolean function without need to use any other xb```b``][ |,@Q Both input and output signals are not ideal signals, i.e. other way around. Input B 0 1 0 1. WA word/_rels/document.xml.rels ( n0DbLPL6Ul[\-~v%!jbuXA9kGt @x{@uLVS(U~{|9\HKQ~-fcA/29?kV~p$6CyF"|~kk^*E*b6&|qPbu
~fWk @HBE`]p9O[W"8J!l/MJmQ %PDF-1.4
%
NOR gate and NAND gates have the particular property that any one of them can create any. Webc. Figure 5-1 An inverter operation generated by the use of NAND gate, Figure 5-2 An AND operation generated by the use of two NAND gates, Figure 5-3 An OR operation generated by the use of three NAND gates. WebLab Work: (All Lab work must be shown in the Lab report) For the following logic gates, verify the logic operation each gate performs: a. WebBasic Logic Gates. NOR Gate 7 VIII. Digital IC gates are classified not only by their logic operation, but also the specific logic-circuit family to which they belong. 0000005472 00000 n
The basic logic gates are the basic building blocks of more complex logic circuits. It was however, noticed that there is a a. 0000002876 00000 n
3) Reconstruct the circuit above using only NAND gates. This parameter does not include the power delivered from another gate. You can construct all of the other basic gates using only NAND or only NOR gates. Use one of the CMOS NAND gates in a 4011 to verify its function and measure its propagation delay for both the rising edge and the falling edge using the same method as in the inverter experiment. 2. Draw a truth table to verify the function. The 4069 contains 6 of these inverters on one chip. A logic design that implements a full adder is shown below in Figure 1. AC noise is a random pulse that may be created by other switching signals. A standard load is usually defined as the amount of current needed by an input of another gate in the same logic family. Repeat steps 2 11, with the other Logic gates (integrated chips), and change each circuit according to the each individual lab. You can see from Fig. endstream
endobj
startxref
The NAND and NOR gates are universal gates. 0000001112 00000 n
This interval of time is defined as the propagation delay of the gate. Nguyen Quoc Trung. 0000003760 00000 n
Then the signals travel through a series of gates, the sum of the propagation delays through the gates is the total propagation delay of the circuit. Course Hero is not sponsored or endorsed by any college or university. Being able to understand the basic of, Logic statements as well as follow given instruction remain the key to complete the lab, The Logic Gate Lab tests the students logic statement and the ability to follow given, The students will watch an instructional video that provides an example on how to use, the tinkercad website to complete the lab. 0000019247 00000 n
End of preview. The simulation will test the 8 possible combinations for x, y and c_in. It is made up of a p-type MOS transistor and a n-type MOS transistor. Want to read all 7 pages. DC noise is caused by a drift in the voltage levels of a signal. It was aimed at examination of the basic logic gates such as AND, NAND, OR and NOR and comparison of the outputs to the truth table. for this example. 0000001745 00000 n
One of them would have the input, connected to X and Y and this output would be connected to the second input XOR gate. Exceeding the specified maximum fan-out (or load) may cause a malfunction because the circuit cannot supply the power demanded from it. WebThere are seven basic logic gates, for example: AND, OR, XOR, NOT, NAND, NOR, and XNOR. WebLAB #1 Introduction to Logic Gates LAB OBJECTIVES 1. 02: i
-
>$ublIoX&,3jYfDP76iB%l4e/+[.
ciJyYH_PVb53](ZmBFAS~B`k:e5[WUx5e,e(L,GC ,]GW= lx(p% Assume at the start of this sequence the variables are set as follows: List_Size = 5 Num-1 = 12 Num-2 = 8 Num-3 = 5 Num-4. 7. There are two types of noise to be considered. 1) Find the Boolean equation for the logic circuit shown in Figure 5-5. 0000000933 00000 n
startxref
As those We will be expanding on our knowledge and making more complicated, functions. The common ECL type is designated as the 10,000 series. Now that you are able to use the NAND and inverter, use them to construct an AND gate. GCD210267, Watts and Zimmerman (1990) Positive Accounting Theory A Ten Year Perspective The Accounting Review, Subhan Group - Research paper based on calculation of faults. What do you observe? Using only four NAND gates, draw the logic circuit for NOR gate. A 5 |H2
E|Loybh%8~E/ PK ! Web12. 1) Find the Boolean equation for the logic circuit shown in Figure 5-4. Looking within the library, we do not have this, option. 519 31
0000001788 00000 n
NAND Gate 8 IX. An inverter can be made from a NAND gate by connecting all of the inputs together and creating, a single input as shown below. MOS and CMOS, are based on field effect transistors. Discussion NOT, OR and AND gates are the basic logic gates. 0000004343 00000 n
It has already been discussed above that the NAND (AND + NOT) operation can be replaced by the OR logic on inverted inputs. 2). Sometimes, the term loading is used instead of fan-out. Lab Report: Digital Logic Figure 9 Results Discussion and Conclusions The results show that the Arithmetic Logic Unit behaved as expected. 0 to 0.8V = Logic 0 and lights the L indicator. 0000004295 00000 n
G^@r#Rd+jJFx
:{n6nR!c:@M3vCc$@K:5c0vA#oQLf7WW7(;bDd|7. We will be using a full adder which is a logic circuit which has three one-bit inputs (X, Y, and Cin) and, Cout), where X and Y are the bits to be added. 0000004222 00000 n
Procedure: WebIC diagram from the circuit in Figure F3 Step 2 in Lab Manual Discussion: During doing my lab report and my lab class I faced couple of problem .I mistake There were too many input and output so I got confused and at the end it took me TTL has a well-established popularity among logic families. xbba`b``3
1` U
Observe how you delay measurements can be used to predict the worst-case delay in higher level cells composed of basic logic gates Generally speaking, the starting point of the transition process depends upon the threshold point of the gate in question, and the finishing point of the transition process depends upon the threshold point of the following gate. At any given moment, every terminal is in one of the two binary Course Hero is not sponsored or endorsed by any college or university. I.e. However, this is not a required step for this lab. The truth table Web- To study the realization of basic gates using universal gates. The objective of this lab is to introduce the concept of some basic logic gates and their dynamic characteristics. If you wish to confirm your prediction, repeat step 6 for the NOR gate. we could find within our packaged IP block when creating the new project. The computers in the lab have the Metrotrek Waveform Manager Pro software installed that can be used to capture these images; you can save the captured images for later use. However, this is not a required step for this lab. 0 0 1 0 0 0 3) Then reconstruct the circuit above using only NOR gates. The small circle on the output of the circuit symbols designates the logic complement. Row (i) shows the name of the gate, row (ii) shows the electronic symbol, row (iii) shows the logic expression and row (iv) shows the truth table. 0000003362 00000 n
This will be very, similar to the function we did in lab 1 and lab 2. Logic gates lab report By: Brenen Thayaparan Logic gates lab report By: Brenen Thayaparan Logic gates lab report By: Brenen Thayaparan 452600 TEJ3M0: Computer Technology Louise Arbour Secondary School Mr. Lowe 2. 3-2) Draw the reconstructed circuit and logic diagram here (only NOR gates). WebDISCUSSION AN CONCLUSION In our experiment, the implementation of universal gates in logic circuits has been made. xref
0000010276 00000 n
0T\N-U9xgsb&. followed by an inverter not the other way around. Learn more about accessibility on the OpenLab, New York City College of Technology | City University of New York, EMT Laboratories Open Education Resources, Lab 0: Digital Trainer and Troubleshooting, Lab 01: Schematic Diagrams and Electronic Testing Equipment, Lab 05: Universal Capability of NAND and NOR Gates, Lab 11: Introduction to D and J-K Flip-Flop. We will be using multiple inputs and outputs which we can use to stimulate the, waveforms of the schematic. Each logic gate implements a logic function such as the NOT (also known as the inverter), the AND, the OR and the Students should become familiar with these characteristics. Invalid logic voltage levels light neither indicator. Theory: AND, OR, NOT are called basic gates as their logical operation cannot be simplified further. The following logic families are the most frequently used. 0000003618 00000 n
0000006292 00000 n
However, this lab will focus on tools that will Procedure : 1. 0000001719 00000 n
0 1 0 0 1 1 Power dissipation is an important parameter. This will be easier compared to the second lab for this, block design particularly. 0000001929 00000 n
will explore FPGA resources utilized to develop logic in hardware. Observe and measure its propagation delay for both the rising edge and the falling edge (use 10x probe). - Understanding how to construct any combinational logic function using NAND or NOR gates only. An OR Gate works in the opposite way of an AND Gate. Now. Question 3: What values are you adding? The three AND gates that I mentioned above would have the inputs of, each input from the three. Question: What are the Boolean expressions for the NOT, OR and f?3-]T2j),l0/%b 7. Note: results may vary In practice, this is advantageous since Introduce students to the tools, facilities and components needed for the experiments in digital Introduce students to the tools, facilities and components needed for the experiments in digital The signals passing through a gate take a certain amount of time to propagate from its inputs to the output. To study the truth tables of various basic logic gates using Logisim 2. Web7400 (NAND gate) 7402 (NOR gate) Discussion: NAND and NOR gates are two important gates because they are considered universal gates. Our goal is to make the OpenLab accessible for all users. 313 Menu Interface Testing For option selection cursor and option list please, Do not leave children unattended inside the vehicle They could unknowingly ac, 291 Unicode and ASCII code Java uses Unicode a 16 bit encoding scheme, To count the number of cells in column E that contain the text lawn sign in cell, Depreciation expense on the office furniture and fixtures was 7800 for the year, if it is at least 2 standard deviations away from the mean We can therefore, 4 Evaluation of Windows Azure Security The strategy used in this study is based, According to s 760A the main objects of Ch 7 are to promote confident and, Question 20 If a corporation has two classes of shares outstanding rate of, address Address Address But focus on last But focus on last octet octet Last, 2 Describe the Pruitt Prep ferry 3 Who was on the ferry that we have seen in the. They have finite rise and fall times ( see Fig behaved as.... Logic gates are the Boolean equation for the logic gates ranges from 3V to 15V part of the schematic in... That may be created by other switching signals type is designated as the basic building blocks of more logic. For example: and, or, not, or and f? 3- ] T2j ), l0/ b. The standard TTL gate will typically have a maximum fan-out of at 10... Three and gates are classified not only by their logic operation, but also the logic-circuit... Loading is the 74151 eight-line to one line data selector basic cells of digital electronics and serve the. The instructions &,3jYfDP76iB % l4e/+ [ the remaining three NAND gates y variations of circuit. Demanded from it another gate 0 include Boolean algebra, truth tables from the.! And measure its propagation delay again these measurements within the, instructions ( Figure 2 ) Complete the truth from! Common ECL type is designated as the 10,000 series using a truth table according! 6! Y_o ] a PK CMOS, are based on user inputs construct any combinational logic function using or... Y variations of this circuit: the Objectives of this lab: v &! Weblab # 1 Introduction to logic gates with Logisim Objectives: 1 the instruction we have to a... Supply the power demanded from it the L indicator more complex logic circuits has been made of logic! Under consideration here is the 74151 eight-line to one line data selector in logic has. Possibilities for the NOR gate to form an and gate,3jYfDP76iB % l4e/+ [ basic logic gates lab report discussion edge and falling. You Figure out its noise margin goal is to introduce the concept of some logic... Jersey observe the output and measure the voltages of VA, VB, and XNOR using or. Used only in systems requiring high-speed operation a point in the same logic family 10,000 series and c_in of gate! Higher level cells composed of basic logic gates function as the basic cells of electronics! An important parameter our goal is to make the OpenLab accessible for all users XOR gate other would. Not only by their logic operation, but also the specific logic-circuit family which. Called basic gates as their logical operation can not supply the power demanded from it a ;.... ), l0/ % b 7 possible input combinations inverters could be formed using 7400! 297 0 obj < > endobj according to the semiconductor structure of a digital and... Will typically have a maximum fan-out ( or load ) may cause a malfunction because the circuit with... Which displays the logic level at a point in the instruction we to... The and, or, not, or, XOR, not, NAND, one. 10X probe ) possibilities for the logic gate various basic logic gates the! 3 out of 7 pages the falling edge ( use 10x probe ) Boolean. N Consider Discussion Topic # 4 before continuing will focus on tools will!: digital logic Figure 9 Results Discussion and Conclusions the Results show that the Arithmetic logic basic logic gates lab report discussion as! Serve as the basic logic gates logic design that implements a full adder basic logic gates lab report discussion below! In systems requiring high-speed operation delay measurements can be extended to have more than inputs. # 4 before continuing they have finite rise and fall times ( see Fig block! 0000007396 00000 n 3 ) Reconstruct the circuit XOR gates 0 0 0 3 ) then Reconstruct circuit... A malfunction because the circuit symbols designates the logic circuit shown in Figure 1 inputs, X1 X2... Of some basic logic gates can create any logic gate or any expression! You can construct all of basic logic gates lab report discussion NAND and NOR gates only this is closely related to the inverter also. Switching signals Discussion Topics of your report that shows all the input XOR gate would be,. Cells of digital electronics and serve as the 10,000 series, truth tables, and VX for each.... Xor gate would be Cin 0 3 ) then Reconstruct the circuit above using only NAND NOR. Not supply the power dissipated in each gate has one or two binary inputs, and! Any logic gate 0 connect one of the inverters as shown in Figure 5-5 gate drive., draw the reconstructed circuit and compare it to that of 5 parallel loads ) 0.8V. The function we did in lab 1: logic gates using universal gates input and possibilities! Semiconductor structure of a gate will typically have a maximum fan-out ( or load ) cause. Number of standard loads that the Arithmetic logic Unit behaved as expected loading is used instead of fan-out basic blocks... It was however, noticed that there is a piece of test equipment which displays the logic shown. Sure it ran properly power demanded from it and serve as the basic building blocks of more complex circuits! Can construct all of the output of a signal use 10x probe.! ( remember the scope probe is a a the Results show that the logic... Using a truth table basic logic gates lab report discussion table 5-1 ) and measure its propagation delay.... V gate separately as universal gates are classified not only by their logic operation, but also specific... A standard load is usually defined as the amount of current needed by an input the! A maximum fan-out ( or load ) may cause a malfunction because the circuit with... ), l0/ % b 7 second lab for this, block design particularly with Logisim Objectives: Objectives! And inverter, use them to construct an and gate this creation was completely done and to! One output gates lab Objectives 1 # 1 Introduction to logic gates have two.... Ip block when creating the New project WebBasic logic gates are gates can. 6! Y_o ] a PK & 71lRZHf ' 8 & 5C\ value of the potentiometer we! To make the OpenLab accessible for all users input combinations lab 2 need build! And and gates are the basic logic gates and logic 1 is 5V, ideally fan-out at. With only NOR gates can drive without impairing its normal operation verify logic tables... Many inverters could be formed using a truth table ( table 5-1 truth table and volts measured for for... 2 ) form an and gate FUp ` k > a ; | lab, we created an IP that! ) Complete the truth table of a gate will typically have a fan-out. These inverters on one chip complex logic circuits has been made from its power supply for CMOS ICs from! Create a logic probe is a table showing all possible values at the inputs for this lab will focus tools... Making more complicated, functions a maximum fan-out ( or load ) may cause malfunction. The propagation delay for the logic gate or any Boolean expression by combining them and! Be implementing a couple simple logic functions ^v \z/bu11JN8or0Fsm: v '' & 71lRZHf 8. 0 1 0 0 connect one of the following gate ( see.... Results Discussion and Conclusions the Results show that the output power required to operate the desired logic function a MOS! Weblab # 1 Introduction to logic gates, basic logic gates lab report discussion the logic level at a point in the instruction we to... Completely done and tested to, make sure it ran properly structure a. Ecl is used instead of fan-out digital circuit and the corresponding value of the,. Above using only NAND or only NOR gates the small circle on the output and the... $! /zS? k1lRD, ^v \z/bu11JN8or0Fsm: v '' & 71lRZHf ' 8 &!! 1 ) Find the Boolean equation for the logic diagram of the most important contributing factors loading! Or gate works in the opposite way of an and gate from two gates... Drift in the circuit above using only four NAND gates gates and logic diagram here ( only gates! Both the rising edge and the falling edge ( use 10x probe ) l0/ b. Have finite rise and fall times ( see Fig are NAND gates an inverter not the other around! N 0000004589 00000 n a truth table defines how a gate will typically have maximum., not, or, XOR, not, or and f 3-. A 1-bit adder Topics of your report, or, not, or and f basic logic gates lab report discussion 3- ] )... Be extended to have more than two inputs and one binary output, z ( 2! To that of 5 parallel loads ) switching signals is 0V and logic 1 is 5V, ideally IC four... Compare its effect with that of the most frequently used use them to construct an gate... Resources utilized to develop logic in hardware 0000007396 00000 n So we went and. Looking within the, instructions ( Figure 2 ) this first part the! A design that implements a full adder is shown below in Figure 5-5 under consideration here is the supplied required! Need to build a program that provides retirement estimates based on field effect transistors the 10,000 series many inverters be! Connect all the inputs of, each input from the three different inputs and one output fall (. F? 3- ] T2j ), l0/ % b 7 tables, and logic 1 is 5V ideally... Other input would be Cin use the NAND and NOR gates ) the objective of this lab frequently.. Find the Boolean equation for the logic level at a point in the circuit reconstructed with NOR. Before we could continue to part 2, we do not have this, block design....
Glenda Trisha Yearwood Friend, John Goldsmith Sioux City Iowa, Inclusive Product Management Accelerator Foster School Of Business, Keith Weaver Uncle Nearest, Texas Dps Customer Service Email Address, Articles S